Most fabrication schemes for memory cell devices incorporating high epsilon materials utilize an electrically conductive diffusion barrier material between the bottom electrode and the silicon contact to prevent (i) contact loss (which may occur if silicon reacts with oxygen diffusing through the bottom electrode during capacitor dielectric deposition to form an electrically insulating layer between the silicon contact and the bottom electrode), and (ii) silicon diffusion to the top surface of the bottom electrode, where the silicon may oxidize to form an undesirable low epsilon layer between the bottom electrode and the memory cell dielectric. The dual requirements that the barrier material be oxidation-resistant (if not electrically conductive in oxidized form) as well as a barrier to both oxygen and silicon diffusion can be quite limiting. For example, TiN and TaN, both viewed as good barriers to silicon diffusion, are not oxidation resistant enough to survive certain types of dielectric processing conditions when used as barriers under Pt electrode layers. In particular, TiN and TaN do not survive the annealing conditions (600-700.degree. C., 760 Torr O.sub.2, 1-2 min) typically used in the preparation of high-epsilon materials by sol-gel techniques.
U.S. Pat. No. 5,381,302 which issued on Jan. 10, 1995 to G. S. Sandhu and P. C. Fazan describes barrier layers that can be used between bottom electrodes of non-oxidizing materials (such as Pt) or conductive oxide materials (such as RuO.sub.2) and contact layers to silicon consisting of Ti, W, Co, Ta, Mo, or their silicides. The barrier layer materials may be refractory metals, conductive metal oxides, and metal nitrides, including Ta, TiN, TaN, Ti, RuO.sub.2, and Ru. Their structures thus contain two layers (a barrier layer and a contact layer) between the bottom electrode and the silicon contact area.
A different approach to the lack of completely suitable barrier materials has been to form a multilayered barrier structure consisting of two or more barrier materials, each barrier material possessing some (but not all) of the desired barrier layer properties. For example, a bilayer barrier structure might consist of an oxidation resistant top layer in contact with the bottom electrode, and an oxidizable diffusion barrier as a bottom layer. U.S. Pat. No. 5,504,041 which issued on Apr. 2, 1996 to S. R. Summerfelt describes such a barrier structure. The oxidation resistant barrier layer may be an exotic nitride such as TiAlN, and the oxidizable diffusion barrier may be a refractory metal, a silicide, or a nitride (such as TiN). Bottom electrode materials described include platinum, palladium, rhenium, rhodium, ruthenium oxide, tin oxide, indium oxide, rhenium oxide, osmium oxide, rhodium oxide, iridium oxide, and combinations thereof.
Still another category of barrier layer materials consists of noble-metal-insulator-alloys such as Pt, Pd, Ru, Re, and Rh alloyed with Si--O or Si--N to form compounds such as Pt--Si--N, Pt--Si--O, Pd--Si--N, Pd--Si--O, etc. These materials are described in European Patent Application EP0698918A1 (S. R. Summerfelt et al.) published on Feb. 28, 1996, and are intended for use as 5-20 .ANG. layers between an oxidizable layer that is substantially conductive and unoxidized, and an oxygen stable layer (such as Pt). These barrier materials are conceptualized as consisting of small particles of noble metal embedded in an oxide or nitride dielectric matrix, with barrier layer conductivity is attributed to tunneling currents between the noble metal particles. Barrier layers of the desired thickness are deposited by reactive sputtering (using, for example, a noble metal silicide target and a low pressure gas mixture of Ar and O.sub.2).
Buried, oxygen-containing barrier layers have been previously described by various authors in connection with the undesirable effects of these layers in slowing or stopping desired silicide formation. For example, reliable cobalt silicide (CoSi.sub.2) formation by the reaction of Co with a silicon substrate is reported to require native-oxide-free silicon and high purity Co (see, for example, S. P. Muraka, "Applications of CoSi.sub.2 to VLSI and ULSI," in Mat. Res. Soc. Symp. Proc., Vol. 320, pp. 3-13, (1994)).
In another example, the effect of oxygen on the formation of platinum silicide from the reaction of Pt with a silicon substrate is reported to depend on Pt morphology and deposition conditions (C. Harder et al., "Morphology Dependent Platinum Silicide Formation in Oxygen Ambients", Phys. Stat. Sol. A Vol. 146 pp. 385-392 (1994)). These references are typical in that incomplete silicide formation is regarded as an undesirable consequence of oxygen contamination, and as something to be avoided.
It is therefore an object of this invention to provide a new type of barrier layer for electrode structures used in the fabrication of devices containing high-epsilon dielectric materials, such as ferroelectric or paraelectric materials.
It is a further object of this invention to teach the use of buried diffusion barriers at the stopped reaction front between silicided and unreacted noble metal formed at the silicide/noble metal reaction front formed when noble metals on silicon or silicon-contributing substrates are annealed in oxygen-containing ambients.
It is a further object of this invention to provide methods and structures for the incorporation of the disclosed buried diffusion barriers into memory devices or capacitors containing high-epsilon dielectric materials.